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[VHDL-FPGA-Verilog] NANDFlashcontrolandFIFOcontrol

Description: 实现NAND Flash块的控制存取以及同步的FIFO的控制 verilog 代码-NAND Flash control access and control of the synchronous FIFO verilog code
Platform: | Size: 6144 | Author: alliance | Hits:

[VHDL-FPGA-Verilog] 5-verilog-programs

Description: the file contains 5 verilog source codes 1. varying pulses 2. DRAM 3. FIFO 4. UART 5. 16 bit divider
Platform: | Size: 5120 | Author: Srinath | Hits:

[VHDL-FPGA-Verilog] Example1

Description: fifo verilog hdl along with test bench its hardware
Platform: | Size: 3072 | Author: zakirmj | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 采用verilog语言的fifo设计。用notpad编辑-Verilog language fifo design. Edited using notpad
Platform: | Size: 1024 | Author: 王亚梅 | Hits:

[VHDL-FPGA-Verilog] 10_100m_ethernet-fifo

Description: 本源码源自于网络，采用verilog编写完成10M以太网到100M以太网的FIFO转化。-The source from the network, using verilog written 10M Ethernet 100M Ethernet FIFO conversion.
Platform: | Size: 487424 | Author: 张居林 | Hits:

[Software Engineering] fifo_module

Description: verilog 语言写的FIFO历程，可以很好参考。 -The write FIFO verilog language course, a good reference.
Platform: | Size: 539648 | Author: wns | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: FIFO is accomplished with the code which is written using the language of verilog.FIFO is the means of first output while first input
Platform: | Size: 62464 | Author: LI | Hits:

[VHDL-FPGA-Verilog] async-fifo

Description: Verilog codes for asynchrounous fifo design
Platform: | Size: 1024 | Author: pravat | Hits:

[source in ebook] FIFO

Description: 是用verilog HDL写的基于FIFO的串口发送机的设计，很详细的代码，很值得学习，已经验证通过-With verilog HDL based on FIFO serial transmitter design, write code, it is worth learning, has been verified by.
Platform: | Size: 359424 | Author: 张阳 | Hits:

[Other] fifo-code

Description: Verilog代码：同步\异步FIFO。包含格雷码计数器.-Verilog code: syncronous\asyncourous FIFO. containing gray counter.
Platform: | Size: 3072 | Author: 王文 | Hits:

[VHDL-FPGA-Verilog] FIFO-and-CAM

Description: verilog code for gray counter,synchronous and asynchronous fifo
Platform: | Size: 25600 | Author: Abhijeet | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 用verilog做的FIFO程序，仿真通过-FIFO procedures to do with verilog simulation by
Platform: | Size: 516096 | Author: hr | Hits:

[Software Engineering] fifo

Description: 这篇文档主要是描述了fifo的作用，里面有用verilog写的源码，及其综合后的结果-This document mainly describes the role of the FIFO inside useful verilog to write source code, and its consolidated results
Platform: | Size: 410624 | Author: 王慧 | Hits:

[Other] fifo

Description: FPGA Verilog语言编写的fifo模块-The fifo module of FPGA Verilog language
Platform: | Size: 13312 | Author: songshiqun | Hits:

[VHDL-FPGA-Verilog] sync-and-asyn_FIFO_verilog

Description: 同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料-Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references
Platform: | Size: 1715200 | Author: gt | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 将ROM的正弦波数据输入FIFO存储器，然后输出，有modelsim仿真波形-Verilog FIFO ROM mif sine
Platform: | Size: 6605824 | Author: xiadafang | Hits:

[Documents] FIFO-[Compatibility-Mode]

Description: fifo specification for designing verilog
Platform: | Size: 534528 | Author: ram | Hits:

[VHDL-FPGA-Verilog] uartfifo

Description: 一个基于verilog的fifo的例子，由数据产生模块产生数据传到fifo中，然后同过发送模块将数据发到上位机上。-One based on the fifo verilog example, by the data generation module generates data to the fifo, and then sent over the same module sends data to the host computer.
Platform: | Size: 661504 | Author: 陈栋磊 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 基于FPGA的8位fifo 1s发送10个8位数据，采用的是verilog 编程语言，入门，方便各位学习-Eight fifo based on FPGA 1 s sent 10 8 bits of data, USES is verilog programming language, introduction, convenient for you to learn
Platform: | Size: 5357568 | Author: 西大楼107 | Hits:

[Internet-Network] FIFO

Description: sample verilog FIFO design
Platform: | Size: 2048 | Author: luttie | Hits:
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